1. Technical Field
The present invention relates generally to an improved integrated circuit apparatus and method. More specifically, the present invention is directed to an apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance.
2. Description of Related Art
The speed at which modern integrated circuit devices operate has been greatly increasing in recent years. It is often necessary to operate such high speed integrated circuit devices in synchronization with a system clock signal that is at a duty cycle, i.e. the ratio of pulse duration to a pulse period, of approximately 50% (a 50/50 duty cycle). Thus, when a clock signal having a duty cycle that is greater than or less than 50% is provided as an input, the integrated circuit device may not perform very well. Duty cycle correction circuits have been developed to address this problem.
Various mechanisms have been devised for providing duty cycle correction circuits. For example, U.S. Patent Application Publications 2002/0140478, 2004/0189364, 2004/0108878, 2004/0075462, 2005/0007168 and U.S. Pat. Nos. 6,844,766; 6,750,689; 6,680,637; 6,583,657; 6,466,071; 6,426,660; and 5,757,218 all describe various circuits for duty cycle correction. In addition, European patents EP1139569B1 and EP1146644A2 and U.S. patent application Ser. No. 10/970,284 describe other types of duty cycle correction circuitry. However, all of these circuits are targeted at achieving a fixed duty cycle value for all conditions, e.g., a 50% duty cycle.
Having a fixed duty cycle may not necessarily result in optimal operating conditions for an integrated circuit device. For example, for optimal performance at a lowered voltage, arrays may need a non-50% duty cycle and may actually need a varying duty cycle. That is, because operational conditions may change, e.g., process (e.g., doping, threshold voltage, mobility, gate oxide thickness, etc. variations across a single wafer and across multiple wafers), voltage, temperature, frequency, etc., a fixed duty cycle may not lead to the optimal performance of the integrated circuit device under all conditions.